1. Field of the Invention
The invention relates in general to floorplanning during design of integrated circuits and more particularly, to use of estimated substrate noise as a constraint during floorplanning.
2. Description of the Related Art
With the increasing levels of integration in chip design, more SOCs are being developed that have digital, analog and RF functions integrated on a single chip substrate. Furthermore, in the deep submicron regime signal integrity issues are increasingly becoming more critical. One of the most significant signal integrity problems in mixed signal designs today is the handling of noise coupled through the common substrate caused by power supply fluctuations due to simultaneous switching of digital cells. See, S. Ponnapalli, N. Verghese, W. K. Chu and G. Coram,” Preventing a Noisequake: Substrate analysis identifies Potential problems in Mixed Signal and RF designs,” IEEE Circuits and Devices, Vol. 17, No. 6, November 2001, pp. 19-28; and M. Heijningen, M. Badaroglu, S. Donnay, M. Engels and I. Bolsens, “High-level simulation of substrate noise generation including power supply noise coupling,” Proc. of IEEE DAC, pp. 738-743, Los Angeles, Calif. June 2000. The main sources of noise injection to the substrate are noise due to digital switching including noise on the ground contacts and on VDD contacts due to switching transients. Researchers have further extended substrate-coupling analysis to floorplanning and placement domains. See, S. Mitra, R. A. Rutenbar, L. R. Carley and D. J. Allstot, “Substrate-Aware Mixed-Signal Macro-Cell Placement in WRIGHT,” Proc. IEEE Customer Integrated Circuits Conf, May 1994, pp. 24.2.1-24.2.4; S. Zhao, K. Roy and C. K. Koh, “Decoupling Capacitance Allocation and Its Application to Power-Supply Noise-Aware Floorplanning,” IEEE Trans. Computer-Aided Design, vol. 21, no. 1, January 2002, pp. 81-92; and W. Kao and W. K. Chu, “Noise constraint driven placement for Mixed Signal Designs,” 2003 International Symposium Circuits and Systems, Bangkok, Thailand, May 25-28, 2003, pp. 712-715.
FIG. 1 is an illustrative perspective view of a mixed-signal integrated circuit that includes a digital subsystem and an analog subsystem and that also includes a cross-section view of the IC substrate. The digital and analog subsystems are physically separated in different circuit blocks. Even though the digital and analog blocks of the integrated circuit (IC) may be separated by relatively large distances, they are nevertheless electrically coupled through a shared substrate. The substrate is a conductive medium vulnerable to a phenomenon called “substrate noise” or “substrate coupling”. Substrate noise can result in un-intended interaction between the digital and analog components of a chip through the underlying silicon substrate. Analog systems generally lack the degree of noise immunity of digital circuits, and the substrate coupling noise can degrade analog performance.
Digital circuits typically operate with two discrete voltages, one corresponding to logic 0 and another corresponding to logic 1. Usually, the logic 1 value is encoded as the power supply voltage (or VDD), and logic 0 is encoded as the ground voltage (or 0, or VSS) in CMOS digital chips. During circuit operation, the signals on the digital portion switch from logic 1 to logic 0 or vice versa. In other words, the voltage on the signal line changes from one extreme allowed voltage to the other.
Analog circuits usually operate with voltage values that represent continuous analog behavior rather than switch between discrete voltages. Analog circuit examples include oscillators, Analog-to-Digital and Digital-to-Analog converters, mixers, amplifiers. Analog circuits typically operate with signals that are significantly smaller in amplitude than digital signals. Analog circuits are, therefore, generally more sensitive to effects of substrate noise than are digital circuits.
Substrate noise can cause fluctuations in the voltage potential of the substrate, which can affect CMOS device behavior. For example, it can change the threshold voltage of a CMOS transistor. For a digital circuit, this could result in a small change in the delay of a logic gate. However, for an analog circuit, the effect can be much more severe. For instance, in an amplifier, a change in threshold voltage can change the operating point of the amplifier and significantly reduce the gain. In a filter, it can reduce the noise margin.
Digital circuit switching generates substrate noise through multiple mechanisms. For instance, digital circuit switching results in substrate noise injection to the substrate from the junction of a digitally switching transistor. Also, digital circuit switching results in substrate noise injection due to power supply fluctuations. More noise ordinarily will be injected to the substrate from areas of the IC with a higher density of digital transistors. The power supply rails of an IC are tied at periodic intervals to the substrate using electrical contacts. This ensures that the substrate is kept at a desired potential. Especially in the digital circuit blocks of the chip, significant current is drawn on the power supply rails, and the power supply voltage fluctuates as a function of the switching activity. This voltage fluctuation is imparted to the substrate through the electrical contacts, and gets propagated through the substrate, eventually reaching the analog circuit blocks of the chip. The imparted voltage fluctuations constitute substrate noise. The variation in power supply voltages, and resultant substrate noise, can be exacerbated by inductance of the power supply lines bringing power to the chip, as well as by on-chip inductances.
In a CMOS circuit, electrical contacts comprise n+ and p+ diffusion regions adjacent NMOS or PMOS devices that are used to set the bulk terminal of the device to either ground or VDD depending on device type. When a digital signal transition occurs, a spike of current from the power supply is used to charge the output load. A significant portion of the current is discharged to ground, which the substrate ultimately connects to. In general, noise injection from the power supply fluctuation is a more significant substrate noise source than noise injection from switching transistors.
These discharge currents work in tandem with the parasitics of the power and ground lines to cause ringing in the supplies. However, since the substrate is connected to power and ground through low resistance substrate contacts, any such noise that appears on the power and ground lines appears also directly in the substrate. Once the noise has been injected into the substrate, it can propagate throughout the substrate. Although noise may be attenuated by the resistance of the substrate, it still can reach all areas of the chip. Substrate voltage fluctuations that reach analog transistors can have a detrimental impact upon their operation as described above.
In general terms, a floorplan comprises a data structure that captures the relative positions of objects in a circuit design rather than the actual co-ordinates of their locations in a design. Once a floorpan has been developed, optimization processes can be used to convert objects within the floorplan to geometrical circuit elements at co-ordinate locations. Creation of an initial floorplan ordinarily is performed early in an integrated circuit design flow since the relative locations of objects within a floorplan can influence other processes in the overall design flow. The objects that have their relative positions determined in a floorplan typically represent larger functional units of the design such as Random Access Memory (RAM), Content Addressable Memory (CAM), register arrays, large clock buffers, DC caps and analog circuits such as phase lock loops. Developing a floorplan also may involve creation of portions of a clock distribution network and placing I/O cells and pads, for example. Relative positioning of objects in a floorplan typically is constrained by factors such as preliminary shapes of the objects, an incidence structure (i.e., a netlist) a preliminary environment (e.g., pin positions), timing information for external signals, path delay information and module delay information. These constraints may be applied recursively to develop the floorplan. For example, under one set of constraints, the degree of interconnectivity between objects and their participation in critical paths may have a significant impact upon their relative positions in a floorplan, e.g., two objects that have timing-critical connections are likely to be positioned relatively closer together.
In the past, accurate substrate noise estimates generally were not easily available for use in developing a floorplan early in an integrated circuit design flow. Substrate noise analysis typically involved detailed extraction of the geometries of IC structures such as, wells, contacts, well taps, diffusions and trenches from a design in the form of a resistive or RC network. However, these design details often are not readily available until later in the design flow, and even when available, detailed extraction can be quite expensive in terms of run time and memory requirements.
Thus, there has been a need for improvements in the use of substrate noise estimates as a guide to development of an initial floorplan early in an integrated circuit design flow. The present invention meets this need.